Back-end-of-line (BEOL) interconnects are utilized in integrated circuits to interconnect the individual devices of the circuit (e.g., transistors) together, and for making chip-to-package connections.
However, related art interconnects typically include relatively short crystalline grains. For instance, related art interconnects are typically formed by reacting a metal layer with semiconductor lines that are continuously in contact with the metal layer. During this related art process, silicide nucleates everywhere along the semiconductor lines, which results in a small grain structure.
For ultra-scaled line widths (e.g., interconnects having a line width of approximately 20 nm or less and/or interconnects having a cross-sectional area of less than approximately 100 nm2), these relatively short crystalline grains may result in a relatively large electrical resistance in the interconnects. A significant contributor to the large electrical resistance of related art interconnects is grain boundary scattering.
Additionally, proposed related art methods to achieve relatively longer crystalline grains in the interconnect lines, such as liner engineering and recrystallization anneal methods, still result in interconnects having a large electrical line resistance at ultra-scaled line widths.